PIC16C58B-04/SS【PDF 95/194 页】IC MCU OTP 2KX12 20SSOP

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录3889

91页 92页 93页 94页 [95页]96页 97页 98页 99页

PIC18F2450/4450

DS39760A-page 182

Advance Information

2006 Microchip Technology Inc.

16.8

Use of the CCP1 Trigger

An A/D conversion can be started by the Special Event

Trigger of the CCP1 module. This requires that the

CCP1M3:CCP1M0

bits

(CCP1CON<3:0>)

programmed as ‘1011’ and that the A/D module is

enabled (ADON bit is set). When the trigger occurs, the

GO/DONE bit will be set, starting the A/D acquisition

and conversion and the Timer1 counter will be reset to

zero. Timer1 is reset to automatically repeat the A/D

acquisition period with minimal software overhead

(moving ADRESH:ADRESL to the desired location).

The appropriate analog input channel must be selected

and the minimum acquisition period is either timed by

the user, or an appropriate TACQ time selected before

the Special Event Trigger sets the GO/DONE bit (starts

a conversion).

If the A/D module is not enabled (ADON is cleared), the

Special Event Trigger will be ignored by the A/D

module but will still reset the Timer1 counter.

TABLE 16-2:

REGISTERS ASSOCIATED WITH A/D OPERATION

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

Values

on page

INTCON

GIE/GIEH PEIE/GIEL

TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

PIR1

—

ADIF

RCIF

TXIF

—

CCP1IF

TMR2IF

TMR1IF

PIE1

—

ADIE

RCIE

TXIE

—

CCP1IE

TMR2IE

TMR1IE

IPR1

—

ADIP

RCIP

TXIP

—

CCP1IP

TMR2IP

TMR1IP

PIR2

OSCFIF

—

USBIF

—

HLVDIF

—

PIE2

OSCFIE

—

USBIE

—

HLVDIE

—

IPR2

OSCFIP

—

USBIP

—

HLVDIP

—

ADRESH

A/D Result Register High Byte

ADRESL

A/D Result Register Low Byte

ADCON0

—

CHS3

CHS2

CHS1

CHS0

GO/DONE

ADON

ADCON1

—

VCFG1

VCFG0

PCFG3

PCFG2

PCFG1

PCFG0

ADCON2

ADFM

—

ACQT2

ACQT1

ACQT0

ADCS2

ADCS1

ADCS0

PORTA

—RA6(2)

RA5

RA4

RA3

RA2

RA1

RA0

TRISA

—

TRISA6(2)

TRISA5

TRISA4

TRISA3

TRISA2

TRISA1

TRISA0

PORTB

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

TRISB

TRISB7

TRISB6

TRISB5

TRISB4

TRISB3

TRISB2

TRISB1

TRISB0

LATB

LATB7

LATB6

LATB5

LATB4

LATB3

LATB2

LATB1

LATB0

PORTE

—

—RE3(1,3)

RE2(4)

RE1(4)

RE0(4)

TRISE(4)

—

TRISE2(4) TRISE1(4) TRISE0(4)

LATE(4)

—

—LATE2(4)

LATE1(4)

LATE0(4)

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.

Note 1:

Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).

RA6 and its associated latch and data direction bits are enabled as I/O pins based on oscillator

configuration; otherwise, they are read as ‘0’.

RE3 port bit is available only as an input pin when the MCLRE Configuration bit is ‘0’.

These registers and/or bits are not implemented on 28-pin devices.

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式